1. Field
Aspects in accordance with present invention relate to a bus control system and a semiconductor integrated circuit (IC).
2. Description of Related Art
Buses using various protocols have been used in semiconductor ICs. In recent years, with the aim of improvement in performance, new high-performance buses have been developed. Intellectual properties (IPs) using the new buses have also been developed.
In the development of a system on a chip (SoC), old resources have been re-used in order to reduce the cost and the man power necessary for the development.
However, a bus bridge circuit (bus bridge) that performs protocol conversion is necessary to build IPs using different protocol buses as a single SoC.
When such a bus bridge circuit is used, if a series of access requests (commands) are processed using the normal method, latency is increased. Performance is also degraded because of the increased time involved in exclusively using the two buses.
Therefore, a buffer that temporarily saves data is provided in the bus bridge circuit. An access request from a master circuit is received in the bus bridge circuit, and then the master circuit side is notified of termination of the access request.
After notifying the master circuit side of termination of the access request, the bus bridge circuit converts the access request into an access request that suits a slave side and outputs the converted access request to the slave side. Such a bus bridge circuit is known.
However, when such a technique is used, a process timing mismatch may occur between the different buses.
Japanese Laid-open Patent Publication No. 2000-040071 describes a semiconductor IC with a bus control system including multiple buses in which malfunction of a circuit connected to these buses is avoided.